1. Field of the Invention
The present invention relates generally to A/D converters and converting methods and, more particularly, to an A/D converter having a coarse period and a fine period in operation. The present invention has particular applicability to A/D converters for video signal processing.
2. Description of the Background Art
Conventionally, a converter which converts an analog signal to a digital signal (hereinafter "A/D converter") is widely used for performing digital signal processing on an analog signal. High speed conversion is also required in A/D converters, since high speed digital signal processing is required, for example, in the field of video signal processing.
As suited for high speed conversion, parallel type and serial-parallel type A/D converters have been conventionally known. Generally, the serial-parallel type A/D converters are operable slower than the parallel type converter. However, since it has small power consumption and can be formed within a small region on a semiconductor substrate, that is, suitable for high integration, they are often used in consumer products for the private sector. One example of the serial-parallel type A/D converter is disclosed in the paper entitled "An 8-MHz CMOS Subranging 8-Bit A/D Converter", in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 6, Dec. 1985. It is pointed out that the present invention is preferably applicable to A/D converters having coarse comparison and fine comparison periods in operation, and particularly to the serial-parallel type A/D converter.
FIG. 11 is a block diagram of a serial-parallel type A/D converter showing the background of the present invention. Referring to FIG. 11, an A/D converter 500 includes a reference voltage generating circuit 1 constituted by resistance elements R connected in series, voltage comparators 21 to 23 comparing a potential of an analog input signal Ai with applied reference voltages, a wiring circuit 2 for transmitting a reference voltage to the voltage comparators 21 to 23, an encoder 3 connected to the outputs of the voltage comparators 21 and 23, a multiplexer 4 for multiplexing data provided from the encoder 3 and a timing signal generator 5.
The resistance elements R constituting the reference voltage generating circuit 1 are connected in series between a predetermined reference potential Vref and ground. A variety of reference voltages are generated through common connection nodes F11 to F43 and C1 to C3 of the resistance elements adjacent to one another. The wiring circuit 2 includes three wirings 41 to 43. The wirings 41 to 43 are connected to the reference voltage generating circuit 1 through switching circuits 11 to 14.
Each of the switching circuits 11 to 14 includes three switching elements. Three switching elements in each of the switching circuits 11 to 14 are simultaneously turned on responsive to the corresponding ones of switching control signals S11' to S14' provided from the encoder 3. In other words, one of the switching circuits 11 to 14 is selectively turned on responsive to the switching control signals S11' to S14'.
The wiring 41 in the wiring circuit 2 is connected to the nodes F11, F21, F31 and F41 through the switching circuits 11 to 14, respectively, each at its first switching element The wiring 42 is connected to the nodes F12, F22, F32 and F42 through the switching circuits 11 to 14, respectively, each at its second switching element. The wiring 43 is connected to the nodes F13, F23, F33 and F43 through the switching circuits 11 to 14, respectively, each at its third switching element.
FIG. 12 is a schematic diagram of a circuit of one voltage comparator shown in FIG. 11. Referring to FIG. 12, the voltage comparator 2i is applicable to each of the voltage comparators 21 to 23. The voltage comparator 2i includes a switching circuit 2ia of a preceding stage and a comparing circuit 2ib of a succeeding stage. The switching circuit 2ia is provided with three switching elements 65 to 67 connected together to an output node 68. The switching elements 65 to 67 operate responsive to control signals .phi.0 to .phi.2 generated from the timing signal generator 5 shown in FIG. 11, respectively.
The switching element 65 receives an analog input signal Ai. The switching element 66 receives a coarse comparison voltage Vrc. The switching element 67 receives a fine comparison voltage Vrf. One coarse comparison voltage Vrc is provided through a corresponding one of the nodes F11 to F43 in the reference voltage generating circuit 1. One fine comparison voltage Vrf is provided through a corresponding one of the nodes F11 to F43 in the circuit 1, and of the switching circuits 11 to 14 and the wiring circuit 2.
The comparing circuit 2ib is provided with a capacitor 60 for a voltage comparison, an inverter 63 for determining a comparison result and a switching circuit 64 for initialization in comparison. The switching element 64 is connected across the inverter 63, and operates responsive to the control signal .phi.0 provided from the timing signal generator 5 shown in FIG. 11.
FIG. 13 is a timing chart showing an operation of the voltage comparator shown in FIG. 12. Referring to FIG. 13, a period AZ denotes an initialization period (hereinafter "auto zero period") for initializing a potential of the node 61. A period CC denotes a coarse comparison period during which a comparing operation by means of the coarse comparison voltage Vrc is performed. A period FC denotes a fine comparison period during which fine comparison operation is performed by means of the fine comparison voltage Vrf. The control signal .phi.0 attains a high level in the auto zero period AZ, and a low level in other periods. The control signal .phi.1 attains a high level in the coarse comparison period CC, and attains a low level in other periods. The control signal .phi.2 attains a high level in the fine comparison period FC and a low level in other periods.
Therefore, the switching elements 64 and 65 are turned on in the auto zero period, and are turned off in other periods. The switching element 66 is turned on in the coarse comparison period, and is turned off in other periods. The switching element 67 is turned on in the fine comparison period FC, and turned off in other periods.
FIG. 14 is a characteristic diagram showing an input/output characteristic of the inverter shown in FIG. 12. Referring to FIG. 14, an abscissa shows a change of an input voltage V61 of the inverter 63, and an ordinate shows a change of an output voltage V62 of the inverter 63. A curve T shows an input/output characteristic in the case of the switching element 64 being turned off. When the switching element 64 is turned on, the input/output voltages V61 and V62 must exist on a straight line L. Therefore, when the switching element 64 is turned on, the input/output voltages V61 and V62 of the inverter 63 become a voltage V.sub.BS (hereinafter "balance voltage") determined by the crossing M of the curve T and the straight line L.
Referring to FIGS. 12 to 14, operation of the voltage comparator 2i will be described. First, in the auto zero period AZ, the switching elements 65 and 64 are turned on, and the switching elements 66 and 67 are turned off, whereby a potential of the analog input signal Ai is applied to a node 68 through the switching element 65. The switching element 64 is turned on, whereby a potential of the input node 61 of the inverter 63 is brought to the foregoing balance voltage V.sub.BS. As a result, the capacitor 60 is charged by the voltages of the nodes 68 and 61.
In the coarse comparison period, the switching element 66 is turned on, and the other switching element 65, 67 and 64 are turned off. When the switching element 64 is turned off, an input impedance of the inverter 63 becomes infinitive, whereby an electric charge on the side of the node 61 charged in the auto zero period AZ is held. The coarse comparison voltage Vrc is applied to the node 68 through the switching element 66, so that voltage change (Vrc-Ai) at the node 68 is applied to the input node 61 of the inverter 63. The inverter 63 provides an output signal Src showing a coarse comparison result in response to the potential applied to the input node 61. That is, the inverter 63 provides a low level signal Src in case of Vrc&gt;Ai. In case of Vrc&lt;Ai, the inverter 63 provides a high level signal Src. Thus, operation in the coarse comparison period is completed.
The output signals showing the comparison result in the coarse comparison period are applied to the encoder 3 by each of the voltage comparators 21 to 23 shown in FIG. 11. The encoder 3 provides the switching circuits 11 to 14 with the appropriate switching control signals S11' to S14' according to the comparison result in the coarse comparison period CC. Therefore, one of the switching circuits 11 to 14 is selectively turned on, and the fine comparison voltages based on the coarse comparison result are applied to the voltage comparators 21 to 23 through the wiring circuit 2 in the subsequent fine comparison period FC.
The switching control signals S11' to S14' provided from the encoder 3 are as in the following. It is assumed that coarse comparison voltages Vrc1, Vrc2 and Vrc3 are provided from the nodes C1, C2 and C3 in the reference voltage generating circuit 1, respectively. In case of Ai&lt;Vrc1, the switching control signals S11' to S14' which make only the switching circuit 14 turn on are provided. In case of Vrc1&lt;Ai&lt;Vrc2, the switching control signals which make only the switching circuit 13 turn on are provided. In case of Vrc2&lt;Ai&lt;Vrc3, the switching control signals which make only the switching circuit 12 turn on are provided. In case of Vrc3&lt;Ai, the switching control signals which make only the switching circuit 11 turn on are provided. Briefly, the encoder 3 provides the control signals S11' to S14' as shown in Table 1 below to change the operation state of the switching circuits 11 to 14.
TABLE 1 __________________________________________________________________________ Output Signals of Voltage Switching State Comparators Output Signals of of Switching Voltage Comparator Encoder 3 Circuits 11-14 Case 21 22 23 S11' S12' S13' S14' 11 12 13 14 __________________________________________________________________________ Ai &lt; Vrc1 L L L L L L H OFF OFF OFF ON Vrc1 &lt; Ai &lt; Vrc2 L L H L L H L OFF OFF ON OFF (in case of (H.sup. L .sup. H) (H.sup. L H .sup. L) (ON OFF ON OFF) multi- addressing) Vrc2 &lt; Ai &lt; Vrc3 L H H L H L L OFF ON OFF OFF Vrc3 &lt; Ai H H H H L L L ON OFF OFF OFF __________________________________________________________________________
In the fine comparison period FC, only the switching element 67 is turned on, and other switching elements 65, 66 and 64 are turned off. Therefore, the fine comparison voltage Vrf generated from the reference voltage generating circuit 1 is applied to the node 68 through the switching element 67. In the auto zero period AZ, since electric charge stored in the node 61 is still held, potential change (Vrf-Ai) at the node 68 is transmitted the input node 61 of the inverter 63. The inverter 63 responds to a potential of the input node 61 to provide an output signal Srf showing a fine comparison result. That is, the inverter 63 provides a low level signal Srf in case of Vrf&gt;Ai and provides a high level signal Srf in case of Vrf&lt;Ai.
Therefore, each of the voltage comparators 21 to 23 shown in FIG. 11 applies to the encoder 3 the output signals showing a comparison result in the fine comparison period FC. The encoder 3 encodes the applied signal to apply data De showing the comparison result in the fine comparison period FC to the multiplexer 4. The multiplexer 4 responds to a control signal .phi.m to multiplex data Dc showing the comparison result in the coarse comparison period CC and data Df showing the comparison result in the fine comparison period FC, to provide multiplexed digital data Do. Some examples of the data Dc, Df and Do are shown in FIG. 16.
FIG. 17 is a circuit block diagram of the encoder 3 shown in FIG. 11. Referring to FIG. 17, the encoder 3 includes AND gates 31 to 34, inverters 35 to 37, and a ROM 38. The AND gates 31 to 34 is connected to receive output signals and inverted output signals from the voltage comparators 21 to 23 shown in FIG. 11. The ROM 38 responds to a control signal .phi.e from the timing signal generator 5 shown in FIG. 11 to convert output signals from the AND gates 31 to 34 into digital codes "11", "10", "01" and "00" according to a predetermined rule.
Briefly, the encoder 3 shown in FIG. 17 provides digital codes as shown in Table 2 below in the coarse comparison and the fine comparison, respectively.
TABLE 2 ______________________________________ Output Signals Output Signals Output Signals of Encoder 3 of Encoder 3 Do of in Coarse Comparison in Fine Comparison Multiplexer 4 ______________________________________ 11 11 1111 10 1110 01 1101 00 1100 10 11 1011 10 1010 01 1001 00 1000 01 11 0111 10 0110 01 0101 00 0100 00 11 0011 10 0010 01 0001 00 0000 ______________________________________
In Table 2, output signals of the multiplexer 4 are also shown. The multiplexer 4 sequentially receives output signals, i.e. digital codes, form the encoder 3 in the coarse comparison and the fine comparison to provide the digital codes in parallel, in other words, provide them as simultaneously converted digital data Do.
After the coarse comparison operation, the output signals S11' to S14' of the AND gates 31 to 34 are provided for controlling the switching circuits 11 to 14 shown in FIG. 11.
FIG. 15 is a circuit block diagram of the timing signal generator shown in FIG. 11. Referring to FIG. 15, the timing signal generator 5 includes dividers 151 and 152, delay circuits 153, 154 and 155 and an AND gate 156. The divider 151 receives a reference timing signal SC in A/D conversion. A chrominance signal subcarrier is used as the signal SC, for example, for A/D conversion in video signal processing.
The AND gate 156 receives each of output signals of the dividers 151 and 152. The output signal of the AND gate 156 is provided as the control signal .phi.0. The signal .phi.0 is delayed by the delaying circuit 155, and the delayed signal is provided as the control signal .phi.1. The output signal of the divider 152 is delayed by the delaying circuits 153 and 154, and the delayed signal is provided as the control signal .phi.2. As a result, the control signals .phi.0, .phi.1 and .phi.2 shown in FIG. 13 can be obtained.
FIG. 16 is a timing chart showing conversion operations repeated in the A/D converter shown in FIG. 11. In FIG. 16, conversion operations in three cycles are shown. One conversion operation is performed by an auto zero period AZ1, a coarse comparison period CC1 and a fine comparison period FC1. As a result of the comparison operations in the periods CC1 and FC1, a coarse comparison code Dc1 and a fine comparison code Df1 are sequentially provided as output signal De. The multiplexer 4 provides in parallel the codes Dc1 and Df1 as converted output data Do. Similarly, another conversion operation is performed by periods AZ2, CC2 and FC2. Still another conversion operation is performed by periods AZ3, CC3 and FC3. In FIG. 16, one example of the change of the analog input signal Ai is shown. The abscissa shown in FIG. 16 denotes the passage of time. The output data De of the encoder 3 and the output data Do of the multiplexer 4 are also shown in FIG. 16.
As described above, the switching control signals S11' to S14' provided from the encoder 3 according to the comparison result in the coarse comparison period are continuously provided in the subsequent auto zero period AZ and coarse comparison period CC. For example, as shown in FIG. 16, the switching control signals S11' to S14' based on the comparison result in the coarse comparison period CC1 are continuously provided also in the subsequent auto zero period AZ2 and coarse comparison period CC2 after the fine comparison period FC1. Therefore, one of the switching circuits 11 to 14 designated by the signals S11' to S14' is continuously turned on in the auto zero period AZ2 and the coarse comparison period CC2.
In an A/D converter 500, the encoder 3 provides the switching control signals S11' to S14' which make more than two of the switching circuits 11 to 14 turn on in case of multi-addressing. Therefore, more than two of the switching circuits 11 to 14 are continuously turned on also in the auto zero period AZ2 and the coarse comparison period CC2. When more than two of the switching circuits are turned on, some of the nodes F11 to F43 in the reference voltage generating circuit 1 are shorted through the switching circuits which are turned on and the wiring circuit 2. This causes the level of the coarse comparison voltage generated in the coarse comparison period to change. Therefore, coarse comparison operation in the coarse comparison period CC2 cannot be performed correctly and, consequently, a wrong coarse comparison result is applied from the voltage comparators 21 to 23 to the encoder 3.
For example, an unfavorable level change of the coarse comparison voltage during the coarse comparison period can be explained as follows. FIG. 18 is a graph showing distribution of an output voltage provided from the reference voltage generating circuit 1 in normal operation. Referring to FIG. 18, an abscissa shows positions C1, C2, . . . of the nodes F11, F12, . . . in the reference voltage generating circuit 1 shown in FIG. 11, and an ordinate shows voltage levels at respective nodes. As shown in FIG. 18, in normal operation, that is, when multi-addressing does not occur, the reference voltage generating circuit 1 provides a coarse reference voltage and a fine reference voltage changing on a progressively descending straight line.
On the other hand, in case of multi-addressing, distribution of an output voltage of the reference voltage generating circuit changes as follows. As one example, the case where the potential of the analog input signal Ai applies to the relation Vrc1&lt;Ai&lt;Vrc2 is considered. In this case, the voltage comparators 21, 22 and 23 provide output signals "L", "L" and "H", respectively, in normal operation (see Table 1). However, when multi-addressing occurs, the voltage comparators 21, 22 and 23 provides output signals "H", "L" and "H", respectively, as shown by ( ) in Table 1. As a result, the encoder 3 provides the output signals S11' to S14' of "H", "L", "H" and "L", so that the switching circuits 11 and 13 are turned on, and the switching circuits 12 and 14 are turned off. As a result of the two switching circuits 11 and 13 being conductive, the reference voltage generating circuit 1 generates a reference voltage having voltage distribution shown in FIG. 9.
FIG. 19 is a graph showing distribution of an output voltage of the reference voltage generating circuit 1 in case of multi-addressing. As shown in FIG. 19, in this example, a reference voltage changing successively and uniformly can not obtained, causing false operation during the coarse comparison period.
In addition, the following problems should also be noted. As described above, the fine comparison voltage Vrf is continuously applied to the voltage comparators 21 to 23 in the preceding fine comparison period, the succeeding auto zero period AZ and the coarse comparison period CC. For example, referring to FIG. 16, the fine comparison voltage Vrf1 is continuously applied in the periods FC1, AZ2 and CC2. Similarly, a fine comparison voltage Vrf2 is continuously provided in the periods FC2, AZ3 and CC3.
When the coarse comparison period CC is completed, a new fine comparison voltage Vrf is applied to the voltage comparators 21 to 23. Therefore, when the voltage difference between the new fine comparison voltage Vrf and the old fine comparison voltage Vrf is big, time required for the change of the fine comparison voltage Vrf applied to the voltage comparators 21 to 23 through the wiring circuit 2 becomes long (see the timing chart shown in FIG. 16). This means that the supply of the new fine comparison voltage Vrf to the voltage comparators 21 to 23 is delayed. As a result, the output of the signal showing a fine comparison result from the voltage comparators 21 to 23 is delayed to make the time required for A/D conversion longer.
For example, referring to FIG. 16, when the coarse comparison period CC3 is completed, since a new fine comparison voltage Vrf3 having a big voltage difference (Vrf2-Vrf3) should be applied to the voltage comparators, establishment of the voltage Vrf3 in the voltage comparators is delayed.